A single-ended sense amplifier is typically designed to sense a state of a bitline in a read-only memory or a register file. For example, the read-only memory usually includes a plurality of memory cells arranged in a form of matrix. Each memory cell is coupled to a wordline node and a bitline node, respectively. If the memory cell contains a transistor, the voltage of the bitline node drops toward ground when an input voltage is applied to the wordline node to turn on the transistor.
A conventional sense amplifier for indicating the change of the voltage at the bitline node is shown in FIG. 1. Referring to FIG. 1, the conventional sense amplifier includes an output circuit 1, a precharge circuit 2, and a discharge circuit 3. The output circuit 1 has a data node 4 as the input terminal. The data node 4 is coupled to the precharge circuit 2 and the discharge circuit 3.
The discharge circuit 3 includes an n-channel transistor M6 and an inverter INV0. The inverter INV0 has its input coupled to the bitline node 5 and its output coupled to the gate electrode of the n-channel transistor M6 at the reference node NR. Therefore, the decrease in the voltage level of the bitline node 5 results in the rapid increase of the gate-source voltage of the n-channel transistor M6.
For the output circuit 1, an inverter INV1 senses the state of the data node 4. If the voltage of the data node 4 drops below a threshold voltage for the inverter INV1, the inverter INV1 outputs a logic high. If the voltage of the data node 4 remains above the threshold voltage, the inverter INV1 outputs a logic low. This logic low level turns a p-channel transistor M7 on such that the voltage of the data node 4 remains at or near an external constant voltage source Vcc. In addition, an inverter INV2 is coupled to receive the output of the inverter INV1, and then generates inverted signal as the output voltage V.sub.out.
The precharge circuit 2 includes a p-channel transistor M5 having a source electrode connected to the external constant voltage source Vcc, a drain electrode coupled to the data node 4, and a gate electrode for receiving a precharge signal 6.
The conventional sense amplifier has two modes of operation: precharge and sense modes. During the precharge mode, the precharge signal 6 is low such that the p-channel transistor M5 is turned on. The bitline node 5 is precharged toward an intermediate voltage level between ground and Vcc through the transistors M5 and M6 until the n-channel transistor M6 is turned off. On the other hand, when the precharge signal 6 is high, the sense amplifier is operated in the sense mode with the non-conductive p-channel transistor M5. If the bitline node 5 is pulled low slightly, the voltage level at the reference node NR will move higher, turning on the n-channel transistor M6. As the bitline node 5 is pulled further down, the n-channel transistor M6 is turned on harder and pulls the voltage of the data node 4 low. Since the n-channel If transistor M6 is biased at the edge of conduction after the precharge operation mode, the sensing speed of the sense amplifier can be very fast.
However, the noise immunity of the conventional sense amplifier is very poor. Any low-going noise on the bitline node 5 can trigger the sense amplifier. This is due to the fact that the gate-source voltage of the n-channel transistor M6 is just at the edge of the threshold voltage.
As a solution to the noise immunity problem, the sense amplifier with an additional precharge circuit has been disclosed in U.S. Pat. No. 5,495,191, as shown in FIG. 2. Referring to FIG. 2, compared with the above-mentioned sense amplifier shown in FIG. 1, the sense amplifier described in U.S. Pat. No. 5,495,191 further comprises a noise margin circuit 7 coupled to the bitline node 5 and controlled by the precharge signal 6. The noise margin circuit 7 includes a p-channel transistor M15, an n-channel transistor M16, and an inverter INV3 as an additional precharge path. The inverter INV3 is preferably different from the inverter INV0 such that the voltage at a reference node NR1 is higher than the voltage at the reference node NR when the identical bitline voltage is used as the input to both inverters INV0 and INV3. In this manner, the n-channel transistor M16 remains on for a while after the n-channel transistor M6 switches off, and the bitline node 5, therefore, is charged higher to provide a noise margin.
However, the conventional sense amplifier disclosed in U.S. Pat. No. 5,495,191 has two disadvantages. On one hand, due to the arrangement of the noise margin circuit 7, the sense amplifier disclosed in U.S. Pat. No. 5,495,191 occupies an larger area on a semiconductor wafer resulting in the decrease of semiconductor device integration. On the other hand, the inverters INV0 and INV3 both consume static power if the bitline node 5 is not pulled down to ground. Therefore, the static power dissipation is significantly large.